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    首页产品索引MC100EP51

    MC100EP51

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     ECL D Flip-Flop with Reset and Differential Clock

    制造商:ON

    中文数据手册

    产品信息

    The MC10/100EP51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices.
    The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP51 allow the device to be used as a negative edge triggered flip-flop.
    The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to V
    and the CLKbar input will be biased at V
    / 2.
    • 350ps Typical Propagation Delay
    • Maximum Frequency > 3 Ghz Typical
    • PECL Mode Operating Range: V
    • = 3.0 V to 5.5 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -3.0 V to -5.5 V
    • Open Input Default State
    • Safety Clamp on Inputs
    • Pb-Free Packages are Available

    电路图、引脚图和封装图

    在线购买

    型号制造商描述购买
    MC100EP51MNR4GONIC FF D-TYPE SNGL 1BIT 8DFN 立即购买
    MC100EP51DTR2GONIC FF D-TYPE SNGL 1BIT 8TSSOP 立即购买
    MC100EP51DR2GONIC FF D-TYPE SNGL 1BIT 8SOIC 立即购买
    MC100EP51DGONIC FF D-TYPE SNGL 1BIT 8SOIC 立即购买
    MC100EP51DTGONIC FF D-TYPE SNGL 1BIT 8TSSOP 立即购买

    技术资料

    标题类型大小(KB)下载
    AC Characteristics of ECL DevicesPDF896 点击下载
    ECL Clock Distribution TechniquesPDF54 点击下载
    Interfacing Between LVDS and ECLPDF121 点击下载
    Designing with PECL (ECL at +5.0 V)PDF102 点击下载
    The ECL Translator GuidePDF142 点击下载
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
    Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载

    应用案例更多案例

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