The NB3L853141 is a low skew 1:5 LVPECL Clock fanout buffer designed explicitly for low output skew applications. The NB3L853141 features a multiplexed input which can be driven by either a differential or single-ended input to allow for the distribution of a lower speed clock along with the high speed system clock. The SEL pin will select the differential clock inputs, CLK0 & CLK0, when LOW (or left open and pulled LOW by the internal pull-down resistor). When SEL is HIGH, the single-ended CLK1 input is selected. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input.

• CLK0 and CLK0 can Accept Differential LVPECL, LVDS, HCSL,
• LVHSTL, SSTL, LVCMOS
• CLK1 can Accept LVCMOS and LVTTL
• 700 MHz Maximum Clock Output Frequency
• Five Differential LVPECL Clock Outputs
• 30 ps Max. Skew Between Outputs
• 1.5 ns Maximum Propagation Delay
• Operating Range: VCC = 2.375 V to 3.8 V
• Synchronous Clock Enable
• 40C to +85C Ambient Operating Temperature Range