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    首页产品索引NB100LVEP91

    NB100LVEP91

    购买收藏
     Translator, AnyLevel™ Positive Input to NECL Output Voltage

    制造商:ON

    产品信息

    The NB100LVEP91 is a triple input to NECL output translator.The device accepts LVPECL, LVTTL, HSTL, CML or LVDS signals, and translates them to differential -2.5 V / -3.3 V NECL output signals.
    To accomplish the level translation, the LVEP91 requires three power rails.The V
    supply should be connected to the positive supply, and the VEE pin should be connected to the negative power supply.The GNDI pins are connected to the system ground plane.Both V
    and V
    should be bypassed to ground via 0.01 uF capacitors.
    Under open input conditions, the Dbar input will be biased at V
    /2 and the D input will be pulled to GND.This condition will force the Q output to a low, ensuring stability.
    The V
    pin, an internally generated voltage supply, is available to this device only.For single-ended input conditions, the unused differential input is connected to V
    as a switching reference voltage.V
    may also rebias AC coupled inputs.When used, decouple V
    and V
    via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA.When not used, V
    should be left open.
    • Typical Maximum Frequency >2 GHz
    • 430 ps Typical Propagation Delay
    • Operating Range:V
    • = 2.375 V to 3.8 V; V
    • = -2.375 V to -3.8 V; GNDI = 0 V
    • Q Output will default LOW with Inputs Open or at GND
    • Pb-Free Packages are Available

    电路图、引脚图和封装图

    在线购买

    型号制造商描述购买
    NB100LVEP91DWR2GONIC XLATOR TRPL PECL-NECL 20SOIC 立即购买
    NB100LVEP91MNR2GONIC XLATOR TRPL PECL-NECL 24QFN 立即购买
    NB100LVEP91DWGONIC XLATOR TRPL PECL-NECL 20SOIC 立即购买
    NB100LVEP91MNGONIC XLATOR TRPL PECL-NECL 24QFN 立即购买

    技术资料

    标题类型大小(KB)下载
    AC Characteristics of ECL DevicesPDF896 点击下载
    ECL Clock Distribution TechniquesPDF54 点击下载
    Designing with PECL (ECL at +5.0 V)PDF102 点击下载
    The ECL Translator GuidePDF142 点击下载
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
    Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载
    Interfacing with ECLinPSPDF72 点击下载

    应用案例更多案例

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