尊敬的客户:为给您持续提供一对一优质服务,即日起,元器件订单实付商品金额<300元时,该笔订单按2元/SKU加收服务费,感谢您的关注与支持!
    首页产品索引MC10EP29

    MC10EP29

    购买收藏
     3.3 V / 5.0 V ECL Dual Differential Clock/Data D Flip-Flop With Set and Reset

    制造商:ON

    中文数据手册

    产品信息

    The MC10/100EP29 is a dual master-slave flip flop. The device features fully differential Data and Clock inputs as well as outputs. The MC10/100EP29 is functionally equivalent to the MC10/100EL29. Data enters the master latch when the clock is LOW and transfers to the slave upon a positive transition on the clock input.
    The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the Dbar input will pull down to V
    and the Dbar input will bias around V
    /2. The outputs will go to a defined state, however the state will be random based on how the flip flop powers up.
    Both flip flops feature asynchronous, overriding Set and Reset inputs. Note that the Set and Reset inputs cannot both be HIGH simultaneously.
    The V
    pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V
    as a switching reference voltage. V
    may also rebias AC coupled inputs. When used, decouple V
    and V
    via a 0.01uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V
    should be left open.
    The 100 Series Contains Temperature Compensation
    • Maximum Frequency > 3 GHz Typical
    • 500 ps Typical Propagation Delays
    • PECL Mode Operating Range: V
    • = 3.0 V to 5.5 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -3.0 V to -5.5 V
    • Open Input Default State
    • Safety Clamp on Inputs
    • These are Pb−Free Devices

    电路图、引脚图和封装图

    在线购买

    型号制造商描述购买
    MC10EP29MNGONIC FF D-TYPE DUAL 1BIT 20QFN 立即购买
    MC10EP29DTGOND FLIP-FLOP, 10E SERIES, 2-FUNC, 立即购买

    技术资料

    标题类型大小(KB)下载
    AC Characteristics of ECL DevicesPDF896 点击下载
    ECL Clock Distribution TechniquesPDF54 点击下载
    Interfacing Between LVDS and ECLPDF121 点击下载
    Designing with PECL (ECL at +5.0 V)PDF102 点击下载
    The ECL Translator GuidePDF142 点击下载
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
    Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载

    应用案例更多案例

    系列产品索引查看所有产品

    MJ21196MC74ACT374MC14094BMC100LVEL38
    MCP19124MC33262MCP6G01RMCP87030
    MCP131MC33172MCP2200MC74ACT157
    MC10EP01MC74HC595AMJ11016MIC4223
    MC10E156MC10EL51MBD330DWMICRF112
    Copyright ©2012-2024 hqchip.com.All Rights Reserved 粤ICP备14022951号工商网监认证 工商网监 营业执照