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    首页产品索引MC10E016

    MC10E016

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     ECL 8-Bit Synchronous Binary Counter

    制造商:ON

    中文数据手册

    产品信息

    The MC10E/100E016 is a high-speed synchronous, presettable, cascadable 8-bit binary counter. Architecture and operation are the same as the MC10H016 in the MECL 10H family, extended to 8-bits, as shown in the logic symbol.
    The counter features internal feedback of TCbar, gated by the TCLD (terminal count load) pin. When TCLD is LOW (or left open, in which case it is pulled LOW by the internal pull-downs), the TCbar feedback is disabled, and counting proceeds continuously, with TCbar going LOW to indicate an all-one state. When TCLD is HIGH, the TC feedback causes the counter to automatically reload upon TCbar = LOW, thus functioning as a programmable counter. The Q
    outputs do not need to be terminated for the count function to operate properly. To minimize noise and power, unused Q outputs should be left unterminated.
    The 100 series contains temperature compensation.
    • 700MHz Min. Count Frequency
    • 1000ps CLK to Q, TCbar
    • Internal TCbar Feedback (Gated)
    • 8-Bit
    • Fully Synchronous Counting and TCbar Generation
    • Asynchronous Master Reset
    • PECL Mode Operating Range: V
    • = 4.2 V to 5.7 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -4.2 V to -5.7 V
    • Internal Input Pulldown Resistors
    • ESD Protection: > 2 kV HBM, > 200 V MM
    • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
    • Moisture Sensitivity Level 1
    • For Additional Information, see Application Note AND8003/D
    • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
    • Transistor Count = 592 devices
    • Pb-Free Packages are Available

    电路图、引脚图和封装图

    在线购买

    型号制造商描述购买
    MC10E016FNR2GONIC COUNTER 8BIT SYNC ECL 28PLCC 立即购买
    MC10E016FNGONIC COUNTER 8BIT SYNC ECL 28PLCC 立即购买

    技术资料

    标题类型大小(KB)下载
    AC Characteristics of ECL DevicesPDF896 点击下载
    ECL Clock Distribution TechniquesPDF54 点击下载
    Interfacing Between LVDS and ECLPDF121 点击下载
    Designing with PECL (ECL at +5.0 V)PDF102 点击下载
    The ECL Translator GuidePDF142 点击下载
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
    Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载
    Interfacing with ECLinPSPDF72 点击下载

    应用案例更多案例

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