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首页产品索引MC100LVEL37

MC100LVEL37

购买收藏
4 Differential, ÷1 / ÷2, 3.3 V

制造商:ON

产品信息

The MC100LVEL37 is a fully differential 1:4 fanout buffer. The device offers two outputs at1 of the input frequency, and two outputs at2 of the input frequency. The Low Output-Output Skew of the device makes it ideal for distributing 1x and 1/2x frequency synchronous signals.
The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the CLKn input will pull down to V
.The CLKnbar input will bias around V
/2 and the Qn output will go LOW.
  • 700ps Typical Propagation Delays
  • 50 ps Maximum Output-Output Skews
  • ESD Protection: >2 KV HBM, >200 V MM
  • The 100 Series Contains Temperature Compensation
  • PECL Mode Operating Range: V
  • = 3.0 V to 3.8 V with V
  • = 0 V
  • NECL Mode Operating Range: V
  • = 0 V with V
  • = -3.0 V to -3.8 V
  • Internal Input Pulldown Resistors
  • Qn Output will Default LOW with Inputs Open or at VEE
  • Qn Output will Default LOW with Inputs Open or at V
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
  • Transistor Count = 256 devices
  • Pb-Free Packages are Available

电路图、引脚图和封装图

在线购买

型号制造商描述购买
MC100LVEL37DWGONClock Fanout Buffer (Distribution), Divider, Multiplexer IC 1GHz 20-SOIC (0.295", 7.50mm Width) 立即购买
MC100LVEL37DWR2GONIC CLK BUFFER 2:4 1GHZ 20SOIC 立即购买

技术资料

标题类型大小(KB)下载
AC Characteristics of ECL DevicesPDF896 点击下载
ECL Clock Distribution TechniquesPDF54 点击下载
Interfacing Between LVDS and ECLPDF121 点击下载
Designing with PECL (ECL at +5.0 V)PDF102 点击下载
The ECL Translator GuidePDF142 点击下载
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载

应用案例更多案例

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