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    首页产品索引MC100EPT25

    MC100EPT25

    购买收藏
     Translator, Differential LVECL / ECL to LVTTL

    制造商:ON

    中文数据手册

    产品信息

    The MC100EPT25 is a Differential LVECL/ECL to LVTTL translator. This device requires +3.3V, -3.3V to -5.2V, and ground. The small outline 8-lead SOIC package and the single gate of the EPT25 make it ideal for applications which require the translation of a clock or data signal.
    The V
    output allows the EPT25 to also be used in a single-ended input mode. In this mode the V
    output is tied to the D input for a inverting buffer or the Dbar input for a non-inverting buffer. If used, the V
    pin should be bypassed to ground with at least a 0.01 µF capacitor.
    • 1.1ns Typical Propagation Delay
    • Maximum Frequency > 275 MHz Typical
    • Operating Range: V
    • = 3.0 V to 3.6 V; V
    • = -5.5 V to -3.0 V; GND = 0 V
    • 24mA TTL outputs
    • Q Output will default LOW with inputs open or at GND
    • V
    • Output
    • Open Input Default State
    • Safety Clamp on Inputs
    • Pb-Free Packages are Available

    电路图、引脚图和封装图

    在线购买

    型号制造商描述购买
    MC100EPT25DTR2GONMixed Signal Translator Unidirectional 1 Circuit 1 Channel 8-TSSOP 立即购买
    MC100EPT25DR2GONIC XLATOR LVECL/ECL-LVTTL 8-SOIC 立即购买
    MC100EPT25MNR4GONTRANSLATOR ECL TO LVTTL 8-DFN 立即购买
    MC100EPT25DTGONIC XLATOR ECL-LVTTL DIFF 8TSSOP 立即购买
    MC100EPT25DGONIC XLATOR ECL-LVTTL DIFF 8SOIC 立即购买

    技术资料

    标题类型大小(KB)下载
    AC Characteristics of ECL DevicesPDF896 点击下载
    ECL Clock Distribution TechniquesPDF54 点击下载
    Interfacing Between LVDS and ECLPDF121 点击下载
    Designing with PECL (ECL at +5.0 V)PDF102 点击下载
    The ECL Translator GuidePDF142 点击下载
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
    Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载

    应用案例更多案例

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