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首页产品索引MC100EP210S

MC100EP210S

购买收藏
5 Differential, Dual LVDS, 2.5 V

制造商:ON

产品信息

The MC100EP210S is a low skew 1-to-5 dual differential driver, designed with LVDS clock distribution in mind. The LVDS or LVPECL input signals are differential and the signal is fanned out to five identical differential LVDS outputs. The EP210S specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. Two internal 50-ohm resistors are provided across the inputs. For LVDS inputs, VTA and VTB pins should be unconnected. For LVPECL inputs, VTA and VTB pins should be connected to the V
(V
- 2.0 V) supply.
Designers can take advantage of the EP210S performance to distribute low skew LVDS clocks across the backplane or the board.
Special considerations are required for differential inputs under No Signal conditions to prevent instability.
  • 20 ps Typical Output-to-Output Skew
  • 85 ps Typical Device-to-Device Skew
  • 550 ps Typical Propagation Delay
  • The 100 Series contains temperature compensation.
  • Maximum Frequency > 1 Ghz
  • Operating Range: V
  • = 2.375 V to 2.625 V with V
  • = 0 V
  • Internal 50Ω Input Termination Resistors
  • LVDS Input/Output Compatible
  • Pb-Free Packages are Available

电路图、引脚图和封装图

在线购买

型号制造商描述购买
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MC100EP210SMNR4GONClock Fanout Buffer (Distribution) IC 1GHz 32-VFQFN Exposed Pad 立即购买
MC100EP210SFAR2GONClock Fanout Buffer (Distribution) IC 1GHz 32-LQFP 立即购买
MC100EP210SFAGONIC CLK BUFFER 1:5 1GHZ 32LQFP 立即购买

技术资料

标题类型大小(KB)下载
AC Characteristics of ECL DevicesPDF896 点击下载
ECL Clock Distribution TechniquesPDF54 点击下载
Interfacing Between LVDS and ECLPDF121 点击下载
Designing with PECL (ECL at +5.0 V)PDF102 点击下载
The ECL Translator GuidePDF142 点击下载
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载

应用案例更多案例

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