尊敬的客户:为给您持续提供一对一优质服务,即日起,元器件订单实付商品金额<300元时,该笔订单按2元/SKU加收服务费,感谢您的关注与支持!
    首页产品索引MC100EP116

    MC100EP116

    购买收藏
     Differential Line Receiver / Driver

    制造商:ON

    中文数据手册

    产品信息

    The MC10EP116/100EP116 is a 6-bit differential line receiver based on the EP16 device. The 3.0GHz bandwidth provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators.
    The V
    pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V
    as a switching reference voltage. V
    may also rebias AC coupled inputs. When used, decouple V
    and V
    via a 0.01uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V
    should be left open.
    The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications.
    The differential inputs have internal clamp structures which will force the Q output of a gate in an open input condition to go to a LOW state. Thus, inputs of unused gates can be left open and will not affect the operation of the rest of the device. Note that the input clamp will take affect only if both inputs fall 2.5V below V
    .
    The 100 Series contains temperature compensation.
    • 260 ps Typical Propagation Delay
    • Maximum Frequency > 3 GHz Typical
    • PECL Mode Operating Range: V
    • = 3.0 V to 5.5 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • =-3.0 V to -5.5 V
    • Open Input Default State
    • Safety Clamp on Inputs
    • Q Output will default LOW with inputs open or at V
    • V
    • Output

    电路图、引脚图和封装图

    在线购买

    型号制造商描述购买
    MC100EP116FAR2GONIC TCVR/DRVR HEX DIFF ECL 32LQFP 立即购买
    MC100EP116FAGONIC RCVR/DRVR HEX DIFF ECL 32LQFP 立即购买

    技术资料

    标题类型大小(KB)下载
    AC Characteristics of ECL DevicesPDF896 点击下载
    ECL Clock Distribution TechniquesPDF54 点击下载
    Interfacing Between LVDS and ECLPDF121 点击下载
    Designing with PECL (ECL at +5.0 V)PDF102 点击下载
    The ECL Translator GuidePDF142 点击下载
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
    Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载

    应用案例更多案例

    系列产品索引查看所有产品

    MIC4451MOCD211MMAT12MIC4100
    MCP47FEB11MCT5210MMMBT918MCP1631
    MC14557BMC74HC4067AMC10E158MJE15032
    MCP47FEB22MCP14E3MJL21194MCP1405
    MC74AC125MCP3905AMC10EL04MC34063
    Copyright ©2012-2024 hqchip.com.All Rights Reserved 粤ICP备14022951号工商网监认证 工商网监 营业执照