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    首页产品索引CDCE62005

    CDCE62005

    购买收藏
    具有集成双路 VCO 的 5/10 路输出时钟发生器/抖动消除器

    制造商:TI

    产品信息

    描述 The CDCE62005 is a high performance clock generator and distributor featuring low output jitter, a high degree of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62005 achieves jitter performance well under 1 ps RMS (10 kHz to 20 MHz integration bandwidth).The CDCE62005 incorporates a synthesizer block with partially integrated loop filter, a clock distribution block including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock distribution block includes five individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (up to 1.5 GHz) and skew relationship via a programmable delay block (note that frequency range depends on operational mode and output format selected). If all outputs are configured in single-ended mode (for example, LVCMOS), the CDCE62005 supports up to ten outputs. Each output can select one of four clock sources to condition and distribute including any of the three clock inputs or the output of the frequency synthesizer. The input block includes two universal differential inputs which support frequencies in the range of 40 kHz to 500 MHz and an auxiliary input that can be configured to connect to an external crystal via an on chip oscillator block.The smart input multiplexer has two modes of operation, manual and automatic. In manual mode, the user selects the synthesizer reference via the SPI interface. In automatic mode, the input multiplexer will automatically select between the highest priority input clock available.特性Superior Performance: Low Noise Clock Generator: 550 fs rms typical (10 kHz to 20 MHz Integration Bandwidth), FC = 100 MHz Low Noise Jitter Cleaner: 2.6 ps rms typical (10 kHz to 20 MHz Integration Bandwidth), FC = 100 MHz Flexible Frequency Planning: 5 Fully Configurable Outputs: LVPECL, LVDS, LVCMOS and Special High Swing Output Modes Unique Dual-VCO Architecture Supports a Wide Tuning Range: 1.750 GHz to 2.356 GHz Output Frequency Ranges from 4.25 MHz to 1.175 GHz in Synthesizer Mode Output Frequency up to 1.5 GHz in Fan-Out Mode Independent Coarse Skew Control on all Outputs High Flexibility: Integrated EEPROM Determines Device Configuration at Power-up Smart Input Multiplexer Automatically Switches Between One of Three Reference Inputs 7-mm × 7-mm 48-Pin VQFN Package (RGZ) –40°C to +85°C Temperature Range

    电路图、引脚图和封装图

    在线购买

    型号制造商描述购买
    CDCE62005RGZTTIIC CLK SYNTH/JITTER CLEANR 48QFN 立即购买
    CDCE62005RGZRTICDCE62005 5/10 OUTPUTS CLOCK GEN 立即购买

    技术资料

    标题类型大小(KB)下载
    CDCE62005 锁相环电路设计与应用PDF545 点击下载
    Clocking Design Guidelines: Unused PinsPDF158 点击下载
    Effects of Clock Spur on High Speed DAC PerformancePDF828 点击下载
    Effects of Clock Noise on High Speed DAC Performance PDF674 点击下载
    Phase Noise Performance and Loop Bandwidth Optimization of CDCE62005PDF556 点击下载
    CDCE62005 Application ReportPDF296 点击下载
    LAN & WAN clock generation and muxing using the CDCE62005PDF2048 点击下载
    CDCE62005 Application ReportPDF2048 点击下载

    应用案例更多案例

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