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首页产品索引NBC12429

NBC12429

购买收藏
 PLL Synthesized Clock Generator, Programmable, 3.3 V / 5.0 V (25 to 400 MHz)

制造商:ON

中文数据手册

产品信息

The NBC12429 and NBC12429A are general purpose, PLL based synthesized clock sources. The VCO will operate over a frequency range of 200 MHz to 400 MHz. The VCO frequency is sent to the N-output divider, where it can be configured to provide division ratios of 1, 2, 4, or 8. The VCO and output frequency can be programmed using the parallel or serial interfaces to the configuration logic. Output frequency steps of 1.0 MHz can be achieved using a 16 MHz crystal, depending on the output dividers. The PLL loop filter is fully integrated and does not require any external components.The NBC12429 is specified to operate across the commercial temperature range.The NBC12429A is specified to operate across the industrial temperature range.
  • Best-in-Class Output Jitter Performance, ±20 ps Peak-to-Peak
  • 25 MHz to 400 MHz Programmable Differential PECL Outputs
  • Fully Integrated Phase-Locked Loop with Internal Loop Filter
  • Parallel Interface for Programming Counter and Output Dividers During Power-Up
  • Minimal Frequency Overshoot
  • Serial 3-Wire Programming Interface
  • Parallel Interface for Power-Up
  • Crystal Oscillator Interface
  • Operating Range: VCC = 3.0 V to 5.5 V
  • CMOS and TTL Compatible Inputs
  • Drop-in Replacement for Motorola MC12429
  • Pb-Free Packages are Available

在线购买

型号制造商描述购买
NBC12429AFNGONIC CLOCK SYNTH 25-400MHZ 28-PLCC 立即购买
NBC12429AFNR2GONCLOCK GENERATOR, 400MHZ, CMOS, P 立即购买
NBC12429AFAGONIC CLOCK SYNTH 25-400MHZ 32-LQFP 立即购买
NBC12429FNGONCLOCK GENERATOR, 400MHZ, CMOS, P 立即购买
NBC12429AMNR4GONCLOCK GENERATOR, 400MHZ, CMOS 立即购买
NBC12429FAGONIC CLK PLL SYNC 25-400MHZ 32LQFP 立即购买

技术资料

标题类型大小(KB)下载
A Comparison of the NBC12429 and MC12429 Programmable PLL Clock SynthesizersPDF34 点击下载
PLL Synthesized Clock Generator, 3.3 V / 5 V Programmable, (25 to 400 MHz)PDF272 点击下载
AC Characteristics of ECL DevicesPDF896 点击下载
IBIS Model for nbc12429fn 3.3VUNKNOW40 点击下载
ECL Clock Distribution TechniquesPDF54 点击下载
Interfacing Between LVDS and ECLPDF121 点击下载
Designing with PECL (ECL at +5.0 V)PDF102 点击下载
The ECL Translator GuidePDF142 点击下载

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