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    首页产品索引NB7N017M

    NB7N017M

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     8-bit Divider with CML Output

    制造商:ON

    中文数据手册

    产品信息

    The NB7N017M is a high speed 8 bit dual modulusprogrammable divider/prescaler with 16 mA CML outputs capable of switching at input frequencies greater than 3.5 GHz. The CML output structure contains internal 50 ohm source termination resistor to VCC. The device generates 400 mV output amplitude with 50 ohm receiver resistor to VCC. This I/O structure enables easy implementation of the NB7N017M in 50 ohm systems.
    The differential inputs contain 50 ohm termination resistors to VT pads and all differential inputs accept RSECL, ECL, LVDS, LVCMOS, LVTTL, and CML.
    Internally, the NB7N017M uses a greater than 3.5 GHz 8 bit programmable down counter. A select pin, SEL, is used to select between two words, Pa(0:7) and Pb(0:7), that are stored in REGa and REGb respectively. Two parallel load pins, PLa and PLb, are used to load the level triggered programming registers, REGa and REGb,
    respectively. A differential clock enable, CE, pin is available.
    The NB7N017M offers a differential output, TC. Terminal count output, TC, goes high for one clock cycle when the counter has reached the all zeros state. To reduce output phase noise, TC is retimed with the rising edge triggered latches.
    • Maximum Input Clock Frequency > 3.5 GHz Typical
    • 50 ohm Internal Input and Output Termination Resistors
    • All SingleEnded Control Pins CMOS and PECL/NECL Compatible
    • Counter Programmed Using One of Two Single-Ended Words,Pa and Pb, Stored in REGa and REGb
    • CML Output Level: 400 mV PeakPeak Output with 50 ohm Receiver Resistor to VCC
    • 16 mA CML output with 50 ohm Internal Source Terminationto VCC
    • Differential CLK, CE, and SEL Input
    • Compatible with Existing 3.3 V LVEP, EP, and SG Devices
    • PbFree Packages are Available

    在线购买

    型号制造商描述购买
    NB7N017MMNR2GONPRESCALER, 7N SERIES, 1-FUNC 立即购买
    NB7N017MMNGONIC DIVIDER 8BIT DUAL CML 52-QFN 立即购买

    技术资料

    标题类型大小(KB)下载
    AC Characteristics of ECL DevicesPDF896 点击下载
    ECL Clock Distribution TechniquesPDF54 点击下载
    Designing with PECL (ECL at +5.0 V)PDF102 点击下载
    The ECL Translator GuidePDF142 点击下载
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
    Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载
    Interfacing with ECLinPSPDF72 点击下载

    应用案例更多案例

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