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    首页产品索引NB4L52

    NB4L52

    购买收藏
     2.5 to 5.5 V ECL D Flip-flop w/Differential Reset & Input Termination

    制造商:ON

    中文数据手册

    产品信息

    The NB4L52 is a differential Data and Clock D flip−flop with a differential asynchronous Reset. The differential inputs incorporate internal 50-ohm termination resistors and will accept LVPECL, LVCMOS, LVTTL, CML, or LVDS logic levels. When Clock transitions from Low to High, Data will be transferred to the differential LVPECL outputs. The differential Clock inputs allow the NB4L52 to also be used as a negative edge triggered device. The device is housed in a small 3mm x 3mm 16 pin QFN package.
    • Maximum Input Clock Frequency > 4 GHz Typical
    • 330 ps Typical Propagation Delay
    • 145 ps Typical Rise and Fall Times
    • Differential LVPECL Outputs, 750 mV PeaktoPeak, Typical
    • Operating Range: VCC = 2.375 V to 5.5 V with VEE = 0 V

    在线购买

    型号制造商描述购买
    NB4L52MNR2GONIC FF D-TYPE SNGL 1BIT 16QFN 立即购买
    NB4L52MNGOND FLIP-FLOP, 4L SERIES, 1-FUNC, 立即购买

    技术资料

    标题类型大小(KB)下载
    IBIS Model for the NB4L52MN UNKNOW36 点击下载
    QFN16, 3x3, 0.5PPDF55 点击下载

    应用案例更多案例

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