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    首页产品索引NB3V8312C

    NB3V8312C

    购买收藏
     1-TO-12 LVCMOS/LVTTL

    制造商:ON

    中文数据手册

    产品信息

    The NB3V8312C is a high performance, low skew LVCMOS fanout buffer which can distribute 12 ultra-low jitter clocks from an LVCMOS/LVTTL input up to 250 MHz. The 12 LVCMOS output pins drive 50Ωseries or parallel terminated transmission lines. The outputs can also be disabled to a high impedance (tri-stated) via the OE input, or enabled when High. The NB3V8312C provides an enable input, CLK_EN pin, which synchronously enables or disables the clock outputs while in the LOW state. Since this input is internally synchronized to the input clock, changing only when the input is LOW, potential output glitching or runt pulse generation is eliminated. Separate VDD core and VDDO output supplies allow the output buffers to operate at the same supply as the VDD (VDD = VDDO) or from a lower supply voltage. Compared to single-supply operation, dual supply operation enables lower power consumption and output-level compatibility. The VDD core supply voltage can be set to 3.3 V, 2.5 V or 1.8 V, while the VDDO output supply voltage can be set to 3.3 V, 2.5 V, or 1.8 V, with the constraint that VDD >/= VDDO.
    • VDD core supply voltage can be set to 3.3 V, 2.5 V or 1.8 V
    • VDDO output supply voltage can be set to 3.3 V, 2.5 V, or 1.8 V, with the constraint that VDD >/= VDDO
    • 250 MHz Maximum Clock Frequency
    • Accepts LVCMOS, LVTTL Clock Inputs
    • 12 LVCMOS Clock Outputs
    • 150 ps Max. Skew Between Outputs
    • Temp. Range 40C to +85C
    • 32pin LQFP and QFN Packages
    • Synchronous Clock Enable

    在线购买

    型号制造商描述购买
    NB3V8312CFAGONIC CLK BUFFER 1:12 250MHZ 32LQFP 立即购买
    NB3V8312CMNR4GONClock Fanout Buffer (Distribution) IC 250MHz 32-VFQFN Exposed Pad 立即购买
    NB3V8312CFAR2GONClock Fanout Buffer (Distribution) IC 250MHz 32-LQFP 立即购买
    NB3V8312CMNGONClock Fanout Buffer (Distribution) IC 250MHz 32-VFQFN Exposed Pad 立即购买

    技术资料

    标题类型大小(KB)下载
    Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载
    Clock Generation and Clock and Data Marking and Ordering Information GuidePDF71 点击下载
    Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)PDF40 点击下载
    Ultra-Low Jitter, Low Skew 1:12 LVCMOS/LVTTL Fanout BufferPDF153 点击下载
    Phase Noise and Additive Phase Jitter Analysis Using the NB3V8312CPDF542 点击下载
    QFN32, 5x5, 0.5P, 3.1x3.1EPPDF56 点击下载
    NB3V8312C IBIS ModelUNKNOW85 点击下载

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