NB3N1900K

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19 HCSL Clock ZDB/Fanout Buffer for PCIe

制造商：ON

中文数据手册

NB3N1900Kdatasheet.pdf

产品信息

The NB3N1900K differential clock buffers are designed to work inconjunction with a PCIe compliant source clock synthesizer to providepoint−to−point clocks to multiple agents. The device is capable ofdistributing the reference clocks for Intel® QuickPath Interconnect(Intel QPI & UPI), PCIe Gen1, Gen2, Gen3, Gen4. The NB3N1900K internal PLL isoptimized to support 100 MHz and 133 MHz frequency operation.The NB3N1900K supports HCSL output levels.

Fixed Feedback Path for Lowest Input−to−Output Delay
Eight Dedicated OE# Pins for Hardware Control of Outputs
PLL Bypass Configurable for PLL or Fanout Operation
Selectable PLL Bandwidth
Spread Spectrum Compatible: Tracks Input Clock Spreading for LowEMI
SMBus Programmable Configurations
100 MHz and 133 MHz PLL Mode to Meet the Next Generation PCIe Gen2 / Gen 3 /Gen 4 and Intel QPI & UPI Phase Jitter
2 Tri−Level Addresses Selection (Nine SMBUS Addresses)
Cycle−to−Cycle Jitter:
Output−to−Output Skew:
Input−to−Output Delay: Fixed at 0 ps
Input−to−Output Delay Variation:
Phase Jitter: PCIe Gen3
Phase Jitter: PCIe Gen4
Phase Jitter: QPI 9.6GB/s
QFN 72−pin Package, 10 mm x 10 mm
These are Pb−Free Devices

在线购买

型号	制造商	描述	购买
NB3N1900KMNG	ON	3.3 V 100/133 MHZ DIFFERENTIAL 1	立即购买
NB3N1900KMNTWG	ON	IC CLK BUFFER 3.3V 1:19 72QFN	立即购买
NB3N1900KMNTXG	ON	3.3 V 100/133 MHZ DIFFERENTIAL 1	立即购买

技术资料

标题	类型	大小（KB）	下载
QFN72 10x10, 0.5P	PDF	56	点击下载
3.3V 100/133 MHz Zero Delay Buffer/Fanout Buffer for PCIe 1 Input 19 HCSL Differential Outputs	PDF	205	点击下载
NB3N1900K IBIS Model	UNKNOW	72	点击下载
A System Designer"s Guide for Building a PCIe Clock Tree while Addressing Timing Challenges	PDF	179	点击下载
NB3N1900K Evaluation Board User"s Manual	PDF	270	点击下载

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