The NB3L202K is a differential 1:2 Clock fanout buffer withHigh−speed Current Steering Logic (HCSL) outputs. Inputs candirectly accept differential LVPECL, LVDS, and HCSL signals.Single−ended LVPECL, HCSL, LVCMOS, or LVTTL levels areaccepted with a proper external Vth reference supply per Figures 4and 6. The input signal will be translated to HCSL and provides twoidentical copies operating up to 350 MHz.The NB3L202K is optimized for ultra−low phase noise, propagationdelay variation and low output–to–output skew, and is DB200Hcompliant. As such, system designers can take advantage of theNB3L202K’s performance to distribute low skew clocks across thebackplane or the motherboard making it ideal for Clock and Datadistribution applications such as PCI Express, FBDIMM, Networking,Mobile Computing, Gigabit Ethernet, etc.Output drive current is set by connecting a 475resistor fromIREF (Pin 10) to GND per Figure 11. Outputs can also interface toLVDS receivers when terminated per Figure 12.

• Maximum Input Clock Frequency > 350 MHz
• 2.5 V ±5% / 3.3 V ±10% Supply Voltage Operation
• 2 HCSL Outputs
• DB200H Compliant
• Individual OE Control Pin for Each Bank of Outputs
• 100 ps Max Output−to−Output Skew Performance
• 1 ns Typical Propagation Delay
• 500 ps Typical Rise and Fall Times
• 80 fs Maximum Additive Phase Jitter RMS