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    首页产品索引NB100LVEP221

    NB100LVEP221

    购买收藏
    20 Differential, HSTL / ECL / PECL, 2.5 V / 3.3 V

    制造商:ON

    产品信息

    The NB100LVEP221 is a low skew 2:1:20 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The two clock inputs are differential ECL/PECL; CLK1/CLK1bar can also receive HSTL signal levels. The LVPECL input signals can be either differential or single-ended (if the V
    output is used).
    The LVEP221 specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device and from device to device.
    To ensure tightest skew, both sides of differential outputs should be terminated identically into 50 ohms even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew.
    The NB100LVEP221, as with most other ECL devices, can be operated from a positive V
    supply in LVPECL mode. This allows the LVEP221 to be used for high performance clock distribution in +3.3 V or +2.5 V systems. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For more information on PECL terminations, designers should refer to Application Note AND8020/D.
    The V
    pin, an internally generated voltage supply, is available to this device only. For single-ended LVPECL input conditions, the unused differential input is connected to V
    as a switching reference voltage. V
    may also rebias AC coupled inputs. When used, decouple V
    and V
    via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V
    should be left open.
    Single-ended CLK input operation is limited to V
    >/= 3.0 V in LVPECL mode, or V
  • 15 ps Typical Output-to-Output Skew
  • 40 ps Typical Device-to-Device Skew
  • Jitter Less than 2 ps RMS
  • Maximum Frequency > 1.0 Ghz Typical
  • V
  • Output
  • 540 ps Typical Propagation Delay
  • LVPECL and HSTL Mode Operating Range: V
  • = 2.375 V to 3.8 V with V
  • = 0 V
  • NECL Mode Operating Range: V
  • = 0 V with V
  • = -2.375 V to -3.8 V
  • Q Output will Default Low with Inputs Open or at V
  • 电路图、引脚图和封装图

    在线购买

    型号制造商描述购买
    NB100LVEP221MNGONIC CLK BUFFER 2:20 1GHZ 52QFN 立即购买
    NB100LVEP221MNRGONIC CLK BUFFER 2:20 1GHZ 52QFN 立即购买

    技术资料

    标题类型大小(KB)下载
    AC Characteristics of ECL DevicesPDF896 点击下载
    ECL Clock Distribution TechniquesPDF54 点击下载
    Interfacing Between LVDS and ECLPDF121 点击下载
    Designing with PECL (ECL at +5.0 V)PDF102 点击下载
    The ECL Translator GuidePDF142 点击下载
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
    Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载

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