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    首页产品索引MC10EP31

    MC10EP31

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     3.3 V / 5.0 V ECL D Flip-Flop with Set and Reset

    制造商:ON

    中文数据手册

    产品信息

    The MC10/100EP31 is a D flip-flop with set and reset. The device is pin and functionally equivalent to the EL31 and LVEL31 devices. With AC performance much faster than the EL31 and LVEL31 devices, the EP31 is ideal for applications requiring the fastest AC performance available. Both set and reset inputs are asynchronous, level triggered signals. Data enters the master portion of the flip-flop when CLK is low and is transferred to the slave, and thus the outputs, upon a positive transition of the CLK.
    The 100 Series contains temperature compensation.
    • 340ps Typical Propagation Delay
    • Maximum Frequency > 3 GHz Typical
    • PECL Mode Operating Range: V
    • = 3.0 V to 5.5 V
    • with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V
    • with V
    • = –3.0 V to –5.5 V
    • Open Input Default State
    • Q Output will default LOW with inputs open or at V
    • Pb-Free Packages are Available

    电路图、引脚图和封装图

    在线购买

    型号制造商描述购买
    MC10EP31DGONIC FF D-TYPE SNGL 1BIT 8SOIC 立即购买

    技术资料

    标题类型大小(KB)下载
    AC Characteristics of ECL DevicesPDF896 点击下载
    ECL Clock Distribution TechniquesPDF54 点击下载
    Interfacing Between LVDS and ECLPDF121 点击下载
    Designing with PECL (ECL at +5.0 V)PDF102 点击下载
    The ECL Translator GuidePDF142 点击下载
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
    Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载

    应用案例更多案例

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