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首页产品索引MC10EP17

MC10EP17

购买收藏
 Quad Differential Driver/Receiver

制造商:ON

中文数据手册

产品信息

The MC10/100EP17 is a 4-bit differential line receiver based on the EP16 device. The >3.0 GHz maximum frequency provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators.
The V
pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V
as a switching reference voltage. V
may also rebias AC coupled inputs. When used, decouple V
and V
via a 0.01uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V
should be left open.
The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications.
Inputs of unused gates can be left open and will not affect the operation of the rest of the device. All V
and V
pins must be externally connected to power supply to guarantee proper operation.
The 100 Series contains temperature compensation.
  • 220ps Typical Propagation Delay
  • Maximum Frequency >3.0 GHz Typical
  • PECL Mode Operating Range: V
  • = 3.0 V to 5.5 V with V
  • = 0 V
  • NECL Mode Operating Range: V
  • = 0 V with V
  • = -3.0 V to -5.5 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • Q Output Will Default LOW with Inputs Open or at V
  • V
  • Output
  • Pb-Free Packages are Available

电路图、引脚图和封装图

在线购买

型号制造商描述购买
MC10EP17DTGONDifferential Receiver/Driver IC 20-TSSOP 立即购买

技术资料

标题类型大小(KB)下载
AC Characteristics of ECL DevicesPDF896 点击下载
ECL Clock Distribution TechniquesPDF54 点击下载
Interfacing Between LVDS and ECLPDF121 点击下载
Designing with PECL (ECL at +5.0 V)PDF102 点击下载
The ECL Translator GuidePDF142 点击下载
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载

应用案例更多案例

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