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首页产品索引MC10E116

MC10E116

购买收藏
 Quint Differential Line Receiver

制造商:ON

中文数据手册

产品信息

The MC10E/100E116 is a quint differential line receiver with emitter-follower outputs. For applications which require bandwidths greater than that of the E116, the E416 device may be of interest.
Active current sources plus a deep collector feature of the MOSAIC III process provide the receivers with excellent common-mode noise rejection. Each receiver has a dedicated V
supply lead, providing optimum symmetry and stability.
If both inverting and non-inverting inputs are at an equal potential of > -2.5 V, the receiver does not go to a defined state, but rather current-shares in normal differential amplifier fashion, producing output voltage levels midway between HIGH and LOW, or the device may even oscillate.
The V
pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V
as a switching reference voltage. V
may also rebias AC coupled inputs. When used, decouple V
and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V
should be left open.
The 100 Series contains temperature compensation.
  • 500ps Max. Propagation Delay
  • V
  • Supply Output
  • Dedicated V
  • Pin for Each Receiver
  • PECL Mode Operating Range: V
  • = 4.2 V to 5.7 V with V
  • = 0 V
  • NECL Mode Operating Range: V
  • = 0 V with V
  • = -4.2 V to -5.7 V
  • Output Q
  • will default low when inputs are
  • Internal Input Pulldown Resistors
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • ESD Protection: > 2 KV HBM, > 200 V MM
  • Moisture Sensitivity Level 1
  • For Additional Information, see Application Note AND8003/D
  • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
  • Transistor Count = 98 devices
  • Pb-Free Packages are Available

电路图、引脚图和封装图

在线购买

型号制造商描述购买
MC10E116FNGONIC LINE RCVR QUINT ECL 5V 28PLCC 立即购买
MC10E116FNR2GONIC LINE RECEIVER QUINT 28-PLCC 立即购买

技术资料

标题类型大小(KB)下载
AC Characteristics of ECL DevicesPDF896 点击下载
ECL Clock Distribution TechniquesPDF54 点击下载
Interfacing Between LVDS and ECLPDF121 点击下载
Designing with PECL (ECL at +5.0 V)PDF102 点击下载
The ECL Translator GuidePDF142 点击下载
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载
Interfacing with ECLinPSPDF72 点击下载

应用案例更多案例

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