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    首页产品索引MC100LVEL90

    MC100LVEL90

    购买收藏
     Translator, Triple ECL Input to LVPECL Output

    制造商:ON

    产品信息

    The MC100LVEL90 is a triple ECL to LVPECL translator. The device receives either -3.3 V or -5 V differential ECL signals, determined by the V
    supply level, and translates them to +3.3 V differential LVPECL output signals.
    To accomplish the level translation, the LVEL90 requires three power rails. The V
    supply should be connected to the positive supply, and the V
    pin should be connected to the negative power supply. The GND pins, as expected, are connected to the system ground plane. Both V
    and V
    should be bypassed to ground via 0.015F capacitors.
    Under open input conditions, the Dbar input will be biased at V
    /2 and the D input will be pulled to V
    . This condition will force the Q output to a LOW, ensuring stability.
    The V
    pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V
    as a switching reference voltage.
    may also rebias AC coupled inputs. When used, decouple V
    and V
    via a 0.01 5F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V
    should be left open.
    • 500ps Propagation Delays
    • ESD Protection: >2 kV HBM, >200 V MM
    • The 100 Series Contains Temperature Compensation
    • Operating Range: V
    • = 3.0 V to 3.8 V; V
    • = -3.0 V to -5.5 V; GND= 0 V
    • Internal Input Pulldown Resistors
    • Q Output will Default LOW with Inputs Open or at V
    • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
    • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
    • Transistor Count = 261 devices
    • Pb-Free Packages are Available

    电路图、引脚图和封装图

    在线购买

    型号制造商描述购买
    MC100LVEL90DWR2GONMixed Signal Translator Unidirectional 1 Circuit 3 Channel 20-SOIC 立即购买
    MC100LVEL90DWGONIC XLATOR TRPL ECL-LVPECL 20SOIC 立即购买

    技术资料

    标题类型大小(KB)下载
    AC Characteristics of ECL DevicesPDF896 点击下载
    ECL Clock Distribution TechniquesPDF54 点击下载
    Interfacing Between LVDS and ECLPDF121 点击下载
    Designing with PECL (ECL at +5.0 V)PDF102 点击下载
    The ECL Translator GuidePDF142 点击下载
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
    Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载

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