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    首页产品索引MC100LVEL32

    MC100LVEL32

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     3.3 V ECL ÷2 Divider

    制造商:ON

    产品信息

    The MC100LVEL32 is an integrated w2 divider. The LVEL32 is functionally identical to the EL32, but operates from a 3.3 V supply.
    The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random state; the reset allows for the synchronization of multiple LVEL32's in a system.
    The V
    pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V
    as a switching reference voltage. V
    may also rebias AC coupled inputs. When used, decouple V
    and V
    via a 0.01 5F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V
    should be left open.
    • 510ps Propagation Delay
    • 2.6 GHz Typical Maximum Frequency
    • ESD Protection: >4 KV HBM, >200 V MM
    • The 100 Series Contains Temperature Compensation
    • PECL Mode Operating Range: V
    • = 3.0 V to 3.8 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -3.0 V to -3.8 V
    • Internal Input Pulldown Resistors
    • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
    • Moisture Sensitivity Level 1
    • For Additional Information, see Application Note AND8003/D
    • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
    • Transistor Count = 111 devices
    • Pb-Free Packages are Available

    电路图、引脚图和封装图

    在线购买

    型号制造商描述购买
    MC100LVEL32DTGONCounter IC Divide-by-2 1 Element 1 Bit Positive, Negative 8-TSSOP 立即购买
    MC100LVEL32DTR2GONCounter IC Divide-by-2 1 Element 1 Bit Positive, Negative 8-TSSOP 立即购买
    MC100LVEL32DR2GONCounter IC Divide-by-2 1 Element 1 Bit Positive, Negative 8-SOIC 立即购买
    MC100LVEL32MNR4GONICDIVIDERDIVX23.3V 立即购买
    MC100LVEL32DGONCounter IC Divide-by-2 1 Element 1 Bit Positive, Negative 8-SOIC 立即购买

    技术资料

    标题类型大小(KB)下载
    AC Characteristics of ECL DevicesPDF896 点击下载
    ECL Clock Distribution TechniquesPDF54 点击下载
    Interfacing Between LVDS and ECLPDF121 点击下载
    Designing with PECL (ECL at +5.0 V)PDF102 点击下载
    The ECL Translator GuidePDF142 点击下载
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
    Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载

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