The KSZ8795 is a highly-integrated, Layer 2-managed, 5-port switch with numerous features designed to reduce system cost. It is intended for cost-sensitive applications requiring four 10/100Mbps copper ports and one 10/100/1000Mbps Gigabit uplink port.

The KSZ8795CLX incorporates a small package outline, lowest power consumption with internal biasing, and on-chip termination. Its extensive features set includes enhanced power management, programmable rate limiting and priority ratio, tagged and port-based VLAN, port-based security and ACL rule-based packet filtering technology, quality-of-service (QoS) priority with four queues, management interfaces, enhanced MIB counters, high-performance memory bandwidth, and a shared memory-based switch fabric with non-blocking support.

The KSZ8795CLX provides support for multiple CPU data interfaces to effectively address both current and emerging fast Ethernet and Gigabit Ethernet applications where the port 5 GMAC can be configured to any of GMII, RGMII, MII and RMII modes.

The KSZ8795CLX product is built upon Microchip's industry-leading Ethernet latest analog and digital technology, with features designed to offload host processing and streamline your overall design.
   
- Four integrated 10/100Base-T/TX MAC/PHYs
- One integrated 10/100/1000Base-T/TX GMAC with selectable GMII, RGMII, MII, and RMII interfaces
- Small 80-pin LQFP package

A robust assortment of power-management features including energy-efficient Ethernet (EEE), PME, and wake-on-LAN (WoL) have been designed-in to satisfy energy-efficient environments.All registers in the MAC and PHY units can be managed through the SPI interface. MIIM PHY registers can be accessed through the MDC/MDIO interface.

Microchip's complimentary and confidential LANCheck® online design review service is available for customers who have selected our products for their application design-in. The  is subject to Microchip's  and requires a myMicrochip account.

Integrated 5-port 10/100 Layer-2 switch with Gigabit uplink

  New generation switch with four MACs, one GMAC (for uplink) and four PHYs that are fully compliant with the IEEE 802.3u standard

  10/100Base-T/TX switch system which combines a switch engine, frame buffer management, address lookup table, queue management, MIB counters, MAC, and PHY transceivers

  Rapid spanning tree support (RSTP) for topology management

  Microchip's LinkMD® cable diagnostic capabilities for determining cable opens, shorts, and length

Advanced Switch Capabilities

  IEEE 802.1q VLAN support for up to 128 active VLAN groups (full range 4096 of VLAN IDs)

  Support 802.1x port-based security and MAC-based authentication via access control lists (ACL)

QoS/CoS Packet Prioritization Support

  802.1p, DiffServ-based and Re-mapping of 802.1p priority field, per-port basis on four priority levels

  4 priority queues with dynamic mapping for IEEE 802.1P, IPV4 ToS (DiffServ), IPV6 Traffic Class, etc

  Programmable rate limiting at the ingress and egress ports on a per port basis

Comprehensive Configuration Register Access

  High-speed SPI (4-wire, up to 50MHz) interface to access all internal registers

  MII management (MIIM, MDC/MDIO 2 wire) interface to access all PHY registers per IEEE 802.3 specification

  Control registers configurable on-the-fly

Switch Monitoring Features

  Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or MII/RMII

  MIB counters for fully-compliant statistics gathering (36 MIB counters per port)

Low Power Dissipation

  Full-chip software power-down

  Energy detect power-down (EDPD)

  Support IEEE P802.3az Energy Efficient Ethernet (EEE)

  Wake on LAN (WoL) support